Questa Inspect - Automated Formal Verification

Depth sequential analysis without testbench

Questa Inspect performs complete formal verification of complex sequential logic problems, eliminating the need to create time-consuming testbenches. This speeds up the verification process and identifies bugs that traditional methods might overlook.

Automated formal checks
Automatizes the main rule checks of FPGA design, including initialization, functional issues, and coverage reachability. It automatically synthesizes checks into assertions, simplifying the verification process and improving accuracy.

Easy-to-use debugging environment

With dedicated GUI windows for debugging, Questa Inspect offers targeted structural debugging tools. Designers can visualize problems in real time with intuitive views of schematics, waveforms and source code, ensuring faster troubleshooting.

Integration into existing workflows

Questa Inspect integrates easily with RTL design environments and continuous integration flows, supporting ASIC and FPGA designs. Mixed language support for Verilog, SystemVerilog and VHDL makes it flexible for various development processes.

The graph clearly shows that the debug is the largest consumer of verification time, occupying 46 percent for FPGAs and 41 percent for ASIC designs. This underscores the importance of efficient debugging tools such as Questa Inspect, which can dramatically reduce the time spent in this phase. By automating and simplifying the debugging process, teams can shift their focus to other critical activities, such as testbench development and test planning, improving overall productivity.

Questa Inspect identifies sequential problems deep in designs that are often difficult to trigger and detect with traditional simulation. This ensures that even the most complex bugs are detected early in the design process.

Questa Inspect automates formal checks to identify problems such as uninitialized registers, X-propagation, combinational loops, FSM errors, and inaccessible logic. This ensures complete verification and robust reachability of the coverage without manual intervention.

Questa Inspect offers a comprehensive GUI with debug windows for controls, waveforms, source code, and FSM details. Automatically generated reports simplify the debugging process, enabling users to quickly identify and resolve problems.

With its push-button approach, Questa Inspect allows users to perform thorough checks without writing properties or creating testbenches. Automatic assertion generation reduces manual intervention, allowing designers to focus on critical design issues.

Questa Inspect integrates seamlessly into existing design flows, supporting mixed-language environments (Verilog, SystemVerilog, VHDL) and working with both RTL and netlist designs. It is compatible with continuous integration environments, making it ideal for the verification of ASICs and FPGAs.